Sudip Shekhar

Silicon Photonic (SiP) evanescent field biosensors exhibit promising potentialfor developing low-cost medical diagnostics. With modern siliconprocesses, hundreds of such sensors can be integrated, enabling simultaneousdetection and processing of multiple biomarkers. Most state-of-the-artevanescent field sensors use resonance peak tracking to measure biomoleculeconcentrations. The simplicity of optics in such sensors makes them a perfectcandidate for commercial scalability. However, they require complexprocessing to filter useful information from data distorted by noise and sensorartifacts. Contemporary sensors often rely on discrete computing units,rendering the system expensive and impractical for point-of-care (PoC) applications.Through innovative optics, coherent biosensors have paved the pathwayfor simplified electronics readout. This being said, achieving comparableperformance to peak tracking sensors requires substantial changes in thedesign of coherent electronic readouts.For the global success of evanescent field sensors, it is imperative to integrateon-chip readouts without compromising performance. This thesisaddresses this challenge through two main objectives. Firstly, a hardware-awareon-chip sensor-data processor is implemented for peak tracking evanescentfield sensors, ensuring performance parity with discrete processors. Secondly,an electronic readout system is designed to improve the performanceof coherent biosensors.

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Silicon photonic (SiPh) sensors hold tremendous potential for the advancement of global healthcare. Leveraging mature complementary metal-oxide semiconductor (CMOS) foundry processes, hundreds of SiPh sensors can be integrated into tiny devices, enabling the detection of multiple pathogens, and eliminating the need for expensive in-lab chemical processing. While the performance of SiPh sensors is similar to clinical standards, the implementation costs remain quite high. To realize the potential that SiPh sensor systems hold for global healthcare, their overall cost must be reduced. SiPh sensors typically rely on high-resolution tunable lasers, which remain an expensive off-chip component. This thesis first summarizes alternative optical sources that are used for SiPh sensors. Fixed-wavelength lasers are a low-cost alternative, and benefit from relative ease of coupling to chip. Unfortunately, the corresponding sensor designs are very sensitive to noise. Broadband optical sources are another lower-cost alternative source; however, their use often requires expensive detection equipment. Despite their drawbacks, implementing these alternative optical sources could significantly reduce the overall cost of a SiPh system.Three low-cost SiPh architectures are presented in this thesis: two that use a broadband source, and one that uses a fixed-wavelength laser. The broadband SiPh architectures use a sensor-tracker system, where one component, a microring resonator (MRR) or a Mach-Zehnder interferometer (MZI), acts as a sensor and a second component acts as a tracker (by electrically tracking wavelength shifts). Since wavelength shifts from the sensor can be read as electrical power shifts in the tracker, this system eliminates the need for expensive detection equipment. Sensitivity values of 78.9 nm/RIU (refractive index unit) and 218.5 nm/RIU were obtained, with system limits of detection of 3.4x10^⁻⁴ RIU and 7.7 x10^⁻⁴ RIU for the MRR and MZI designs, respectively.In the fixed-wavelength system, a heater-detector tuning element is placed in the MRR loop. This similarly enables electrical tracking of wavelength shifts, thus reducing the noise sensitivity commonly found in fixed-wavelength systems. Simulation results report sensitivities up to 76 nm/RIU, with calculated intrinsic limits of detection down to 3.8 x10^⁻⁴ RIU. The results obtained demonstrates that high-resolution tunable lasers are not required to achieve high sensor performance.

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The unabated demand for data communication has led to a rapid growth in warehouse-sized datacenters where high-end servers transfer terabytes of data per second between the racks using optical data links. Vertical cavity surface-emitting laser (VCSEL) based optical links are widely popular in such datacenters for short-reach (
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Optical communication networks are the foreseeable solution to meet the increasing demand for high data rates. An important part of a communication network is the network switch that facilitates the routing of data from sources to destinations, from a set of input streams to a set of output streams.Silicon photonics is poised to play a significant role in optical communication networks due to its suitability to build scalable and highly integrated photonic structures and systems, in addition to the use of established fabrication methods inherited from the electronics industry. One of the applications where silicon photonics can play a critical role is in implementing network switches. A Mach-Zehnder interferometer (MZI) is an optical device that is ideally suited to build network switches, as it can be dynamically controlled to achieve high-quality switching of optical signals. However, the performance of silicon photonics devices is sensitive to fluctuations in ambient temperature, fabrication tolerances, and device aging, and MZI devices are no exception. This work describes the factors that degrade the performance of an MZI switch, and then presents an electronic feedback system that monitors and automatically tunes a 1x2 MZI switch to its optimum operating point and compensate for the aforementioned performance-degrading factors. A design for a 2x2 MZI switch monitoring technique is also presented that uses feedforward interferometry to enable more efficient use of the MZI as a switch for two simultaneous optical inputs at different wavelengths, and an electronic feedback and tuning system for such switches is also demonstrated.

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Phase-locked loops (PLLs) are widely used in communication and digital systems to generate high frequency clocks by multiplying a low-frequency reference clock. Scaling of complementary metal-oxide-semiconductor (CMOS) technology over the last decade has benefitted digital circuits by shrinking their size and reducing their power consumption. On the other hand, it has posed challenges for analog design because of the decreasing power supply voltage and output impedance of transistors. Therefore, an all-digital PLL (ADPLL) becomes increasingly preferable over its conventional analog counterparts in terms of area and design flexibility. PLLs employ an oscillator locked to the phase and frequency of the reference clock. An LC oscillator utilizes an inductor (L) to filter noise, but on-chip inductors require large area and need specific thick metal layers for low loss. Compared to LC oscillators, ring oscillators are more suitable for ADPLL implementation since they occupy smaller area and are compatible to digital CMOS processes without a thick-metal layer option. However, the oscillation frequency of a ring oscillator is determined by the propagation delay of the delay-cells, and thereby very susceptible to power supply noise. In fully-integrated systems, switching of large-scale digital circuits can create large supply ripples and degrade the noise performance of the PLL output. Low dropout (LDO) regulators as well as some cancellation techniques have been adopted in prior-art to mitigate the supply sensitivity of ring-oscillator based ADPLLs. However, these techniques suffer from supply voltage headroom, noise penalty, and design complexity. In this thesis, a low-complexity supply-noise-insensitive ADPLL is proposed that does not degrade the supply voltage headroom, and operates over a wide range of supply-noise amplitude. Fabricated in a 65nm CMOS process, the ADPLL achieves ~ 45 mV of tunable supply-noise-insensitive range where the frequency pushing is less than 10%, operating at 850 mV supply. With the tuning range from 1 GHz to 1.4 GHz, the ADPLL achieves 16 ps integrated jitter at 1.25 GHz output frequency and consumes 2.73 mW of power. 

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We show that, in comparison to an inductor, an asymmetric transformercan improve the quality factor (Q) of an inductor-capacitor (LC) tank whenthe tank loss is dominated by the varactor. Near, and at mm-wave frequencies,varactors in complementary metal-oxide-semiconductor (CMOS)processes have significantly lower Q than inductors and transformers. Directlyconnecting a varactor to the core of an LC oscillator lowers tank Q,and the increased ratio of parasitic capacitance to total tank capacitancelimits frequency tuning range (FTR). Instead, magnetically coupling a varactorto the oscillator core using an asymmetric transformer, where the coreis connected to the primary and varactor to the secondary, increases tankQ. Furthermore, it permits doubling the varactor bias range and reducingthe parasitic capacitance seen at the varactor. Thus, both FTR andPhase Noise (PN) are improved simultaneously. Measurement results fortwo prototypes in 65nm CMOS are presented. A 25 GHz Voltage-controlledOscillator (VCO) shows an FTR of 29.8%, a PN of -106.6 dBc/Hz at 1 MHzoffset, and an FTR-inclusive Figure of Merit (FoMT ) of -195.04 dBc/Hz. A60 GHz self-mixing VCO, where the VCO core at 20 GHz is mixed with itscommon-mode 40 GHz tone, shows an FTR of 18.5%, a PN of -98.9 dBc/Hzat 1 MHz offset, and an FoMT of -193.4 dBc/Hz.

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All wireless communication systems so far have employed either time division duplexing (TDD), where the transmitter and receiver share the same frequency band but operate in orthogonal time slots, or frequency division duplexing (FDD), where the time slots are shared but orthogonal frequency bands are used.In order to meet the requirements for the upcoming 5G mobile standards, the concept of simultaneous full-duplex is being actively pursued, where both time slots and frequency bands can be shared between the transmitter and the receiver. The greatest hurdle in achieving full-duplex communication is the self-interference from the transmitter that is several orders of magnitude stronger than the desired signal at the receiver. Realizing such broadband cancellation has been hitherto very challenging, because not only does it demand broadband cancellation in amplitude, phase and group delay of the echo signals, but also require such a cancellation circuit to be linear, low-noise and ultra-compact for a mobile form factor. This work will demonstrate the first self-interference radio-frequency cancellation circuit that achieves an 80 MHz linear time evolution (LTE) cancellation bandwidth in a linear, tunable, compact, and fully monolithic integrated circuit (IC) implementation for such full-duplex radios. A proof-of-concept prototype is realized in 0.13 µm complementary metal oxide semiconductor (CMOS) process that utilizes techniques such as frequency translations and baseband Hilbert transforms to attain a measured 23 dB of self-interference cancellation over an 80MHz signal bandwidth. The entire circuit consumes 34 mW from a 1.2V supply in an active area of just 0.84 mm².

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Optoelectronic links play a key role in data-center, high-performance computing, sensor and biological applications. Photodetectors (PDs) are used at the front end of every optoelectronic receiver (RX). Traditionally, PDs are fabricated in expensive technologies to enhance their performance. However, wirebonding an external PD to a complementary metal-oxide-semiconductor (CMOS) RX or flip-chip assembly results in several issues – increase in manufacturing and packaging cost, possible decrease in yield, additional packaging parasitics degrading the sensitivity of the RX, crosstalk between the bondwires degrading RX performance, requirement for electro-static discharge (ESD) devices, etc. Some of the above problems can be surmounted by fabricating the PD in a CMOS process. However, CMOS PDs have very low responsivity. To improve the responsivity, the PD can be operated in the avalanche region where it has a higher current gain. But there are two major concerns – first, Avalanche PDs (APDs) require high bias voltage for its operation, and second, it is very sensitive to variations in operating conditions. Degradation in the APD performance can reduce RX bandwidth and sensitivity. In this thesis, we present an opto-electrical RX which incorporates on-chip APD, bias generation and stabilization for 850-nm optoelectronic interconnect applications. The proposed receiver consists of CMOS-APD, transimpedance amplifier (TIA), main amplifiers, offset correction loop and 50Ω buffers in the high speed path. APDs are designed and measured to have a -3 dB bandwidth (BW) of 3.5 GHz in 130nm CMOS process, and 6 GHz BW in 65 nm CMOS process, respectively. The electrical -3dB BW of RX, designed and measured in 130nm CMOS process, is approximately 4.5 GHz. A fully integrated APD-RX system is implemented in 130 nm CMOS process that also comprises of a control loop consisting of an analog-to-digital converter (ADC), synthesized controller, digital-to-analog converter (DAC) and voltage booster. The voltage booster biases the APD with a voltage higher than nominal supply voltages in CMOS, and the control loop stabilizes this bias voltage from temperature variations. On-chip APD based RX with bias generation and stabilization have tremendous potential in optoelectronic links due to inherent advantages of high gain, low cost, reduced ground-bounce and bond-wire parasitics.

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The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor and field-programmable gate array (FPGA) systems, PLLs are typically used for clock generation.Although phase-locking is a very mature research topic, its continuous application in modern integrated circuits (ICs) and systems, requires continuous improvement in its performance, power consumption, and manufacturing costs. Analog Type-II PLLs are among the most widely used category of PLLs in CMOS (complementary-metal-oxide-semiconductor) ICs, mainly due to their robustness, superior performance and their well-established theory. However, analog Type-II PLLs require a large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pumps (CPs). All-digital PLLs are also widely used, but they suffer from the strict jitter requirements on time-to-digital converters (TDCs). We propose a Type-I PLL that uses a small LF area, does not require bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies – limited lock-range and large reference spur – are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and to further improve the lock-range and lock-time. A proof-of-concept prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm² in 0.13-μm CMOS and achieves 490 fsrms random jitter, -103.4 dBc/Hz in-band phase-noise, -65 dBc reference spur, 2.5 μs worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.

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