Shahriar Mirabbasi

The full abstract for this thesis is available in the body of the thesis, and will be available when the embargo expires.

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The main focus of this work is on the analysis and design of low-power low-voltage complementary metal-oxide-semiconductor (CMOS) integrated circuits for wirelessly powered implantable systems, in general, and with an emphasis on “Smart Stent” applications. In the context of smart stents, the goal is to collect and transmit sensory data from a stent, for example, the one that is implanted inside an artery or inside the ureter, for clinical diagnosis. The power for the electronic blocks on the “Smart Stent” is harvested from an optimized external radio-frequency (RF) source that enhances the local power density surrounding the implanted stent. As a proof-of-concept design, a commercially available coronary stent is used as the power receiving antenna for the circuits embedded on the implant, and the sys- tem functionality is fulfilled by customized circuit blocks implemented in CMOS technology. Low-power low-voltage circuit blocks are designed to minimize the power consumption of the overall system, and the interface between the stent and the CMOS die is co-designed for improving the in-vitro power transfer efficiency. A CMOS rectifier with a fully on-chip transformer-based tunable matching network is designed in a 0.13-μm CMOS process and the measurement results show that it can generate more than 500 mV DC voltage on a 2 kΩ load when the available power received by the stent is greater than −2 dBm, corresponding to 34% power conversion efficiency (PCE). An output capacitor-less low-dropout regulator (LDO) topology that can operate from a 0.58-to-0.9-V supply is also designed in the same 0.13-μm CMOS process. Furthermore, a low-power 5 GHz Class-D VCO is implemented. With 0.2-V supply voltage, only 280 μW is required by the oscillator core, and a figure of merit (FoM) of 192.5 dBc/Hz can be achieved. To validate the presented circuits and the design methodology, the operation of the complete system that consists of a proposed multi-port external RF source and the “Smart Stent” (stent and the proposed chip) is demonstrated in-vitro. The results of the wireless power transfer experiments show that with 480 mW transmitting power and 53 mm separation distance, more than 350 μW is delivered to the im- planted system.

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With the unprecedented growth in the number of connected devices and demand for larger amount of data as well as higher data rate, there is a need to improve our communication systems to address such demands. Addressing these demands have resulted in devising a roadmap for transition from current 4th generation of communication systems (4G) to the 5th generation (5G) and beyond 5G in the near future. To address the demand for higher data rates, broadening the frequency spectrum of 5G and beyond 5G to millimeter wave bands is being actively pursued. To overcome propagation losses, reduce interferers and improve signal-to-noise ratio, phased-array systems have attracted a lot of attention especially for applications operating in mm-wave bands. In this work, we mainly focus on two important building blocks of phased-array systems, namely, power amplifiers (PAs) and phase shifters.To fulfill the stringent linearity and efficiency requirements of the 5G and beyond 5G systems, a linear and efficient PA is required. We present several design techniques for implementing highly linear and efficient CMOS PAs. The proposed techniques include strategic placement of varactors, a multi-function coplanar-waveguide (CPW)-like power combining structure, and a systematic design approach for the passive networks. A proof-of-concept prototype that operates in the 28 GHz band is designed and fabricated in a 65-nm bulk CMOS process. The design achieves a Psat of 23.2 dBm, output P1dB of 22.7 dBm, and power-added efficiently (PAE) of 35.5%.Next, a continuous-mode 360˚ mm-wave ultra-wideband phase shifter over the frequency range of 10 GHz to 50 GHz is presented. A proof-of-concept prototype is also designed and fabricated in a 65-nm bulk CMOS process. To implement such an ultra-wideband phase shifter, design approaches for several key building blocks including balun and quadrature all-pass filter (QAF) are proposed. These sub-blocks are separately analyzed. To confirm the validity of the proposed techniques, proof-of-concept prototypes have been designed and tested. Particularly, the continuous-mode 360˚ phase shifter prototype achieves ~0.2-dB root-mean square (RMS) amplitude and
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Compressive sensing, as one of computational imaging techniques, employs exposure encoding of cameras. Currently, as coded exposure is not supported monolithically on image sensors, computational cameras rely on discrete optical modulators to implement compressive sensing. In this thesis, we propose image sensor designs that are capable of per-frame spatial-temporal exposure encoding. We propose merging exposure-programmable pixels, which consist of charge modulators and exposure-code memory, into the imager design. Through pixel-wise exposure manipulation in every frame of image capture, compressive sensing and its related imaging applications are extended to the sensor node with significant benefits of high optical throughput, improved power efficiency, and compact footprint.In the design of exposure-programmable pixels, four types of pixel architectures are proposed. The capacitive-transimpedance-amplifier-based pixels are advantageous in sensitivity and charge-transfer speed, while the other two which use active-pixel-sensor-based structures offer a more compact size and circuit simplicity. To exploit the full potential of proposed pixel designs, the image sensor architecture is correspondingly modified as compared to the conventional image sensor designs.To evaluate the feasibility and performance of the proposed designs, two prototype image sensors are fabricated in a CMOS process. From experimental results, both conventional non-intermittent exposure and per-frame spatial-temporal coded exposure are verified. In demonstration of on-chip compressive sensing applications, two examples from high-speed imaging and compressive focal-stack depth sensing are presented. By performing compressive sensing at the sensor level, the CMOS image sensor designs introduced in this work further pave the way to on-chip computational imaging and facilitate implementation of many emerging applications in the machine vision paradigm.

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Over the last decade, integrated circuit technology has witnessed a surge in interest toward millimeter-wave (mm-wave) frequencies (30 to 300 GHz), mainly due to the increasing number of promising applications enabled by and implemented in this frequency band. Imaging and bio-molecular spectroscopy are among the main applications of mm-wave frequencies. The ability to characterize nanostructures could have a dramatic impact on basic research in materials design and biosensing. Many magnetic-resonance (MRI) based imaging techniques used to explore biological structures benefit partly from being carried out at very low temperatures. Lack of transistor models at such low temperatures is a major challenge for circuit design. In the first part of this thesis, we address the fundamentals of signal generation at low temperatures and develop a custom-designed, application-specific signal source for an imaging experiment implemented in a 0.13-µm bipolar/complementary metal-oxide semiconductor (BiCMOS) process. The basics of signal generation outlined in this part can be expanded to include other needs for cryogenic applications.Radio technology has evidenced a rapid evolution with the launch of the analogue cellular systems in 1980s. As technology evolves, so does our expectation on how we could use it. Growing demand for high throughput and capacity on one end, and the ever-increasing desire towards ubiquitous connectivity on the other end, have strained current schemes and standards, calling for alternative novel high capacity systems. To address capacity demands, mm-wave spectrum provides a unique opportunity due to the availability of wider and unpopulated frequency bands which better facilitate high-speed communications. In this context, the emerging 5th Generation Mobile Network (5G) is also expected to use mm-wave bands. However, energy efficiency remains a critical issue for all of these applications and has become an important challenge to deal with in face of higher performance requirements. In the second part of this thesis, we propose circuit solutions and strategies for efficient signal generation at very high-frequency bands and demonstrate state-of-the-art mm-wave signal sources implemented in 65-nm and 0.13-µm CMOS with DC-to-RF efficiencies of around 15%, the highest efficiencies reported to date for CMOS oscillators operating in the vicinity of and beyond 100 GHz.

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Sensors are devices that convert a physical stimulus into an electrical signal. Mechanical stimuli such as touch, pressure, strain and shear are very important for a plethora of applications. A lot of these application areas, including consumer electronics, sports, health care and robotics, require the sensor to be soft, stretchable and even transparent. In this thesis we demonstrate three capacitive sensors that are each an evolution of the preceding version. The first sensor is a flexible, transparent, proximity and touch sensor based on mutual capacitance technology - the conventional technology used in most touch-screen devices. The novelty in this research is the sensor’s ability to operate while being deformed. This is important for applications where the device is expected to experience a bend or stretch while being interacted with such as in a wearable device and smart clothing. The second sensor in this thesis adds the ability to detect pressure and strain to enable its use in further applications. The sensor uses both mutual capacitance and overlap capacitance to detect the range of stimuli mentioned. The dielectric has cylindrical air gaps that enhance the pressure sensitivity. A 4 X 4 array structure is implemented that demonstrates the detection and differentiation of the different stimuli. However, for artificial skin applications, the ability to sense shear is extremely valuable, for example for helping robots grasp objects. The third sensor developed in this thesis is able to detect proximity and light touch similar to the previous iteration, but with 10X increase in pressure sensitivity (1.3% change in capacitance per kPa applied pressure, compared to 0.13% change for the second sensor) and the ability to detect localized shear (2.2% change in capacitance per kPa of shear stress). The novelty is a patterned dielectric architecture with pillars and sliding supports that enable the top surface of the sensor to slide and buckle like real skin and therefore enable the detection of localized shear. All the sensors use readily available materials (silicone, carbon black and/or polyacrylamide), along with conventional molding and bonding techniques and should be easy to produce in large quantities at low cost.

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The aggressive scaling of the CMOS technologies has made it possible to implement denser, cheaper, higher performance and lower power integrated circuits (ICs) for a widespread of applications. Among these applications in various implantable medical devices (IMDs) such as cochlear implants, capsule endoscopy, brain-machine interface, and smart stents, telemonitoring and wireless communication are key functions. The radio-frequency (RF) communication systems for IMDs differ from conventional data-driven radios in various aspects including form factor, power consumption, communication range, and operation manner. The focus of this thesis is on exploring novel circuit- and system-level design techniques for monolithic CMOS wireless event-driven radios intended for miniaturized biomedical implants. To fulfill the stringent power requirement, conventionally various forms of envelope-detection-based receivers are used. However, such receivers suffer from inferior sensitivity and also need calibration or external components, which are not amenable solutions for IMDs. To address these issues, a crystal-less receiver that employs a programmable envelope detector to provide a better trade-off between sensitivity and power consumption is presented. Furthermore, a double-mixing receiver is robust to process, supply voltage and ambient temperature (PVT) variations. By suppressing flicker noise and DC offsets, the proposed architecture while achieving an improved sensitivity eliminates the need for external components and calibration. There are typically three wireless links existing in an implantable radio system, the uplink, the downlink, and the power link. In this work, the up- and down-stream datalinks are realized by exploiting 915 MHz frequency band using time division duplexing (TDD) that is manipulated by a smart control module, while remote power link is realized in the 2.4 GHz band. Without any external components and calibration overhead, the radio is also robust to PVT variations, leading to a low-cost and highly integrated wireless node. To confirm the validity of the proposed technique, proof-of-concept prototypes have been designed and fabricated. All prototype circuits have been implemented in CMOS technology and have been successfully evaluated. The applications of proposed techniques are not limited to IMDs and they can also be used in other applications where energy resources are constrained and/or low power operation with miniaturized size are required.

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Over the last three decades, radio-frequency(RF) Complementary Metal-Oxide-Semiconductor(CMOS) electronics has made a huge impact in our world. Wireless Local Area Networks(WLANs), cellular networks, Global Positioning Systems(GPSs), and Bluetooth are a few examples where the impact of RF CMOS has led to rapid adoption and standardization of the technology. However, there still exists several challenging areas at the intersection of RF and CMOS where new paradigms must be established. This thesis summarizes the research to meet those goals as briefly described here: Research during the past decades provided CMOS solutions to RF applications that utilize the frequency spectrum up to 6 GHz. However, efficient system integration of mm-wave and THz in CMOS is still a challenging task. The THz spectrum is gaining interest due to its wider and less populated available spectrum, as well as its intriguing applications in molecular spectroscopy, imaging, and sensing. This band, although very useful, has been difficult to realize in hardware because of the limitations in CMOS electronics. In the first four chapters of this thesis, we investigate the challenge of implementing signal-sources at mm-wave and sub-THz frequencies using low-cost and versatile CMOS circuits, replacing the existing expensive solutions.Demand for embedded low-power electronics for wireless connectivity is growing due to the rapid proliferation of Internet-of-Things (IoT). Although Wireless Sensor Network(WSN) had been around for decades, some applications such as biomedical monitoring systems require ultra-low-power(ULP) and cost-effective wireless solutions. Research on energy-harvesting systems (e.g., RF energy harvesting, thermoelectric, etc.) and integrated-circuits(IC) bears the promise of medium-reach battery-free wireless connectivity solutions. In Chapters 5 and 6 of this thesis, multiple ULP wireless connectivity solutions for both commercial standards such as Bluetooth Low Energy(BLE) and custom-designed application-specific-radios are proposed and implemented in 40nm and 130nm CMOS technologies, respectively.Finally, application of RF electronics in power-electronics is studied in the last chapter. Although power-management integrated circuit is a well-developed field of research, PMICs still have existing bottlenecks (e.g., die area and output ripple) which can be addressed with the knowledge of RF electronics. In this thesis, feasibility of GHz-range converters is studied.

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Advances in sub-micron complimentary metal-oxide semiconductor (CMOS) technologies have enabled implementation of ultra-low-power circuits and systems for variety of applications including readout systems for capacitive radiation detectors. As state-of-the-art readout systems may integrate thousands of electronic channels on chip, designing low-power and low-noise interface circuits is of great interest. The focus of this work is on developing a design methodology for such readout circuits with an emphasis on interfacing with capacitive sensors, in general, and solid-state radiation detectors, in particular. The critical aspects of the design from analyzing the specifications to noise optimization and circuit design are taken into account and the proposed circuits offer improved performance for the readout system.To facilitate the noise analysis of modern readout systems, the equivalent noise charge equations of the system are derived analytically. The analysis takes into account the stringent requirements of modern readout systems as well as the noise sources associated with deep submicron CMOS technologies. The analysis is based on the EKV (Enz, Krummenacher, and Vittoz) model of MOS transistors which is a model valid for all regions of operation.As a proof of concept, the analysis and design of three low-power and low-noise interface circuits are presented. The proposed circuits are fabricated in a 0.13 um CMOS process. The first interface circuit consists of a novel charge-sensitive amplifier (CSA), a pole-zero cancellation (PZC) circuit, and a 2nd-order programmable pulse shaper. The proposed CSA accepts signals of both polarities, exhibits 111 e-rms noise, and consumes only 37.5 uW. The second interface circuit consists of a CSA, a reset network, a 1st-order shaper, and a PZC circuit. The circuit consumes about 1 mW and exhibits 66 to 101 e-rms noise at different peaking times. The third interface circuit is a mixed-signal design and consists of a CSA with leakage compensation, a 5th-order programmable Gaussian shaper, a peak-detect and hold, a discriminator, and a novel Wilkinson-based digitizer. The circuit consumes 1.97 mW and exhibits 58 e-rms noise. The design performs favourably in terms of power consumption and noise behavior in comparison with similar works in the literature.

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Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and presents implementation of various aspects of such EPDA framework. Various building blocks of silicon-photonic systems are reviewed in the first chapter of the thesis. The review discusses an example of a 60-GHz wireless system based on photonic technology, which could be suitable for the emerging 5th-generation (5G) cellular networks, and also provides design use cases that need to be supported by the EPDA framework.Integrated photonic circuits, which are the building blocks of wireless-photonic systems, will achieve their potential only if designers can efficiently and reliably design, model, simulate, and tune the performance of electro-optical components. The developed EPDA framework supports an integrated optical solver, INTERCONNECT, to provide optical time and frequency domain simulations so that a designer would be able to simulate electrical, optical, and electro-optical circuits using two developed and implemented methodologies: sequential electro-optical simulation and co-simulation. We propose an algorithm to enhance the performance of electronic simulation engines that can be integrated into the EPDA simulation methods such as Harmonic Balance. It will be shown that body-biasing of CMOS transistors can be used as an effective method for tuning the performance of the electronic section of an electro-optical design. This can help designers adjusting the performance of their designs after fabrication. Modelling of electro-optical components is discussed in this thesis; It is shown that some traditional passive components such as inductors, which take a large amount of space in CMOS processes, could be fabricated in the much lower cost photonic process and consequently the overall cost of silicon-photonic systems can be reduced significantly.

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In recent years, the demand for low-cost, high performance, and miniature sized MEMS capacitive inertial sensors (accelerometer/gyroscope) has been steadily increasing. Use MEMS capacitive accelerometer as an example, for high precision applications, the resolution needs to be in the μg range at the frequency of interest. These high performance sensors are now been used in numerous applications that require more demanding specifications. For instance, they found their use in active suspension, adaptive brakes, alarm systems, tilt control, vibration, shock measurements, platform stabilization, inertial measurement units, inertial navigation/guidance, machine control, microgravity measurements, seismology, geophysical sensing, oil-field applications, earthquake detection, tactical missiles, robotics and minimally invasive surgery.The precision in a micro-sensory system is limited by the CMOS electronic interfaces, due to the often higher electrical noise associated with the circuits. Additionally, with the growing popularity for portable devices such as cellular phones and tablets, power consumption also becomes an important factor. Therefore, the dissertation discusses and presents several circuit design techniques that improve important system parameters such as noise and power. Moreover, a design flow is provided at the end of the thesis to demonstrate a systematic approach to design the sensor interface circuits. Three major readout circuit blocks have been designed, built, and tested. The first interface uses a circuit technique such that the overall system is insensitive to parasitic capacitances from the sensing nodes. Moreover, a calibration scheme is used to remove DC offset caused by sensor capacitance mismatch. The second interface uses two circuit design techniques called correlated level shifting (CLS) and chopper stabilization (CS) to reduce the noise and the finite gain error from the operational amplifier (op amp), thereby improving both the noise and power performance of the system. The final interface utilizes a modified CLS technique such that it also serves as a noise and power improving mechanism. The first two readout circuits have been tested and measured experimentally, while the third readout circuit is verified via post-layout simulation.

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In today's Electric Vehicles (EVs) and conventional Combustion Engine Vehicles(CEVs), data communication between electronic control units is accomplished by sending communication signals over dedicated wires. The space requirement, weight, and installation costs for these wires can become significant, especially in electric vehicles of the future, which are highly sophisticated electronic systems. This has motivated research and development activities in the area of Vehicular Power Line Communication (VPLC). VPLC systems reuse power wires inside a vehicle for data communicationpurposes. Thus, they eliminate the need for extra wires dedicated to communication.However, there are several impediments to overcome in order to achieve a reliable and robust VPLC. Many of these challenges originate from inherentproperties of current wirings in vehicles, which are not designed with communication in mind. Therefore, to develop suitable data transmissionequipments, a good understanding of the communication channel characteristics is essential. Considering the importance of proper characterization as a first step towards the design and deployment of VPLC systems, in this work, we have tried to contribute to the available body of knowledge on channel characterization for VPLC in EVs and CEVs. As tangible contributions, we present methodology and results of two measurement campaigns in this thesis. The main outcomes of this part of our research are quantitative statements about Channel Transfer Functions and Access Impedance for two vehicles and discussions of our results in the context of VPLC system design.Building on the results of these measurements, an adaptive impedance matching system is designed to improve the power transmission between VPLC devices and the vehicular power line network, and consequently improve the Signal-to-Noise Ratio (SNR) of the communication system. The adaptive impedance matching system is first behaviorally described in VHDL-AMS and simulated using Cadence™ and then for each unit a circuit design compatible for implementation on an Integrated Circuit (IC) platform is suggested.Tested against the challenges of VPLC observed in our measurement campaigns, the proposed system proved to be capable of significantly improving the reliability of communication over power wires in vehicle.

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Advances in microelectronic technologies have facilitated implementation of leading-edge circuits particularly in the realm of ultra-low-power circuits and systems. The focus of this thesis is on the design of reliable integratedsolutions for telemonitoring of biomedical implants. In particular, we focus on diagnosing in-stent restenosis (re-narrowing) of coronary arteries after angioplasty. To achieve more efficient wireless power delivery, a modifiedversion of conventional medical stent, namely antenna stent or stentenna, is used. In this work, two different systems are designed and fabricated in a 0.13-μm complimentary metal-oxide semiconductor (CMOS) process. The first telemonitoring system converts the capacitive changes of the (pressure) sensors directly to a corresponding frequency change which will betransmitted to the external reader. Unique to this design is the alignment unit which is designed to improve the physical alignment of external inductive antenna with the implanted stentenna for the purpose of wireless power transfer. The system starts operating with the rectified voltage of as low as 500 mV while consuming 4.15 μW, 3.4 μW of which is consumed by the transmitter. The system is designed such that, in alignment mode, the frequency of the pilot signal is directly proportional to the value of the rectifiedsupply voltage. The monitoring unit, start operating from the supply voltage of 870 mV while drawing 111.25 μA. This system has been successfully tested in an in-vitro setup. The measured sensitivity of the system is 555 kHz/fF.This system is capable of detecting capacitance change of as low as 1.3 fF.The sensor interface circuit of the second system consists of a capacitance-to-voltage converter and the transmitter includes a voltage-to-frequency converter.The frequency for the transmitted signal is proportional to the changes of the capacitance of the sensor. Measurement results of a proof-of concept prototype show that the system operates from a harvested supply of as low as 350 mV (from input power of -43.76 dBm at 1.25 GHz) whiledrawing less than 100 nA from its harvested supply. The sensitivity of the system is measured to be 55 kHz/fF.

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The basic concept of radio-frequency identification (RFID) as a means of wireless identification of physical objects has existed for over half a century. However, the technology became economically feasible during the mid-90s mainly due toproliferation of low-cost integrated circuits. Since its emergence, RFID technology has gained extensive attraction and has been used in numerous industrial applications. To facilitate widespread deployment, RFID tags as the backbone of such identification systems have to fulfil two general requirements, namely, low power consumption and small form factor. In this thesis, with an emphasis on power and area efficient architectures, efficient data and power converters as the two major building blocks of sensor-enabled RFID tags are investigated.In the context of data conversion, by using two low-power analog buffers instead of the conventional binary weighted capacitive array, a low-power 8-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an area efficient digital-to-analog converter (DAC) architecture is proposed. Furthermore, time-mode ADC as an alternative area and power-efficient structure is discussed and a highly linear, wide-input-range voltage-to-time converter (VTC) is presented and experimentally evaluated.In the context of efficient power converters, through optimizing the bias voltage of the gate of switching transistors in a conventional differential rectifier, three high-efficiency RF rectifier architectures, namely, gate-boosted, auxiliary-cell biased, and quasi-floating-gate (QFG)-biased rectifiers areproposed. Furthermore, through dynamically adjusting the input capacitance, a dual-band matching approach for RF rectifiers is presented. The proposed QFG-biased rectifier is incorporated and analyzed in a wake-up radio front-end. Also, backscattering method as a power efficient scheme during the transmit mode is studied in the context of biomedical implants. Furthermore, based on the techniques developed for enhancing the efficiency of the rectifier, an ultra-low-power complementary metal-oxide-semiconductor ( CMOS ) voltage-controlled ring oscillator architecture is proposed.The proposed building blocks and systems, namely, ADC, rectifiers, wake-up radio structure, and voltage-controlled ring-oscillator architecture are designed in a 0.13-µm CMOS technology and their performances are verified through post-layout simulation and/or measurement results.

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In ultrasound imaging, capacitive micromachined ultrasonic transducer (CMUT) technology has become a promising alternative to conventional piezoelectric- based technology. This work focuses on various aspects of CMUT-based imaging technologies. In the context of CMUT design and integration with associated electronics, flexible and reliable CMUT models that can be seamlessly simulated with the read-out circuits and provide insights in the system-level performance are of great importance. This work proposes a generic Verilog-AMS model for CMUT sensors that takes into account the non-linearities, dynamic behavior and harmonic resonances of the CMUT. This model is able to provide reliable estimations of the pull-in voltage as well as the resonance frequency and the spring softening effect.To improve the signal-to-noise ratio (SNR), integrating the CMUT transducer with the front-end electronics is critical. Design and implementation of a comprehensive analog front-end system in a 0.8μm high-voltage CMOS technology which includes high-voltage and fast-switching transmitters as well as low-power variable-gain receivers is presented. Co-simulation of the front-end electronics and the CMUT model demonstrates full system functionality. Experimental results of the system at the transmit mode confirm the reliability of this co-simulation. An on-chip adaptive biasing unit (ABU) is also included in the design which aims to improve the CMUT receive sensitivity. The ABU consists of a DC-DC converter to generate a range of bias voltage levels and a digital control unit to select the desired voltage. Co- simulation of the ABU with the Verilog-AMS model confirms the increase in the CMUT sensitivity in receive mode.In the context of CMUT super-resolution imaging, we present the design of a transceiver circuit in a 0.35μm high-voltage CMOS technology that supports both the fundamental and asymmetric modes of operation. The transmitter provides high- voltage pulses to the CMUT electrodes. The receiver includes transimpedance analog adders to add the fundamental mode in-phase signals as well as differential amplifiers to combine the out-of-phase signals of the asymmetric modes. Furthermore, low- power variable-gain stages are included to amplify the resulting signals and facilitate interfacing to the ultrasound imaging machine for additional processing and display. The design functionality is confirmed by experimental results.

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High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal.In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog and digital design techniques to reach a robust operation suited for long-haul optical link communications. Proof-of-concept prototypes of the proposed RX architectures are designed and implemented in 65 nm and 90 nm CMOS processes. The prototypes are successfully tested. Note that although individual performance merits of the each prototype may not necessarily outperform that of the state-of-the-art, however, the prototypes confirm the feasibility of the proposed structure. Furthermore, the proposed architectures can be used at higher data rates particularly if more advanced technologies with higher device transit frequency, (fT), is used.

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Reliable high-temperature analog and mixed-signal CMOS circuits are required for several applications including aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In particular, in this work we focus on the design of key building blocks of a miniature sensor interface system that is intended to operate in a pulp and paper digester and collect and record sensory data such as pressureand temperature along its trajectory within the digester. The temperature inside thedigester can be as high as 180℃.Design considerations and techniques for implementing these building blocks both atcomponent- and circuit-levels are presented. At the component level, techniques fordesigning monolithic resistors with a desired temperature coefficient (TC) are proposed, and an analysis on the effects of design parameters such as resistor length, width and the number of fingers on the TC of such multi-finger resistor structures is presented. Furthermore, since the foundry-provided transistor models are typicallyvalid up to 125℃, various NMOS and PMOS transistors with diff erent sizes are implemented to study their behaviour at high temperature. Based on our observations, a suitable sizing for transistors is suggested for circuits operating up to 200℃. At the circuit-level, several key building blocks such as bias circuits, voltage references and oscillators are designed and proof-of-concept prototypes are implemented in astandard 0.13 ㎛ CMOS process. The operation of the circuits is experimentallyvalidated over the temperature range of interest, namely, 25 to 200℃.Also, a low-complexity resistive and capacitive temperature-compensation techniquesfor high-temperature relaxation oscillators is proposed. Although the temperaturestability of the proposed oscillator (108 ppm/℃) compares favourably with that ofstate-of-the-art designs, it occupies 0.007 mm² which is 2.3 to 114 times smaller thanother comparable designs. Also, the proposed circuit operates reliably up to 200℃(as compared to 125℃ in other designs).Although the proposed techniques are only validated using proof-of-concept prototypes in a 0.13 ㎛ CMOS technology, they are general and our preliminary studies onseveral technologies indicate that the techniques can be implemented in other CMOStechnologies as well.

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Communication systems are essential components of our everyday lives and they facilitate accessing and using the ever-increasing amounts of data that have surrounded us. The main objective of this research is to present solutions at the device, circuit, and system levels for key passive and active circuit building blocks of communication systems, namely, monolithic passive inductors and inductor-based voltage-controlled oscillators (LC-VCOs). These components are almost ubiquitously used in integrated wireless and wireline communication transceivers, as well as other computing devices. Key contributions of this work are as follows: In the context of monolithic inductors, we have studied different inductor structures such as doubly-stacked inductors, vertical inductors, and coupled-rings. We have developed circuit models to accurately estimate their inductance and quality factor. The proposed analytical expressions provide designers with a reasonable estimate of their circuit performance and layout constraints. The result of proposed analyses is verified by the measurement results of test structures implemented in CMOS technology.Regarding LC-VCOs, we have studied the effect of large signal oscillations on such VCOs by developing a mathematical model to solve the non-linear differential equation governing the LC tank circuit. The study shows that the VCO frequency and the amplitude of higher order harmonics are functions of circuit parameters such as the C-V characteristics of the varactor and the oscillation amplitude. Also, a low- power technique to boost the output amplitude of push-push VCOs is introduced. Measurement results of a proof-of-concept prototype test chip in 90-nm CMOS confirm the usefulness of the proposed technique.Finally, at the system level, we present an analytical model to study the effect of coupling between adjacent LC-VCOs closely integrated on the same chip. This is usually the case in high-speed wireline transceivers such as those used in serial links. The proposed model explains the behavior of spurious sidebands as observed in the frequency spectrum of closely-running adjacent links. A redundant frequency mapping scheme is proposed that significantly reduces this coupling effect. Measurement results of a highly packable clock synthesizer in a 65-nm CMOS confirm the validity of the analytical model and the effectiveness of the proposed mapping technique.

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Body biasing is commonly used in digital and low-power analog integrated circuits to adjust the threshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors and to lower the supply voltage. In this work, the application of body biasing to improve the performance of four of the main building blocks of CMOS radio-frequency (RF) front-ends is explored. Here, the body-biasing technique is used in conjunction with other design techniques and provides an extra degree of freedom in the design of CMOS RF front-end building blocks including low-noise amplifiers (LNAs), active down-conversion mixers, voltage-controlled oscillators (VCOs), and power amplifiers (PAs). The performance improvements are mainly related to noise and linearity of these building blocks and have been achieved through adjusting the values of the bulk-source transconductance, the source-bulk capacitance, and the threshold voltage of the MOS transistors. Body biasing is applied in multi-stage LNAs to improve their noise figure and linearity as well as to adjust the gain. Body biasing is used to improve the linearity of active down-conversion mixers with gradual LO switching by enhancing the linearity of the LO stage. Body biasing is used in cross-coupled LC VCOs to improve their phase noise performance by forward body biasing of core transistors which lowers the duty cycle in class-C mode of operation. In active-inductor-based LC VCOs, body biasing is used to increase the tuning range of active inductors and thus the oscillation frequency. Finally, body biasing is in the predistortion stage of class-AB PAs to improve the linearity by compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. In all cases, these improvements are achieved with minimal overhead on circuit-level complexity and power consumption of the overall system. The proposed applications of body-biasing technique are validated through measurements on different proof-of-concept prototypes fabricated in 0.13-µm, 90-nm, and 65-nm CMOS technologies.

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Over the past decade, there have been substantial activities as well as changes in the design of high-speed radio-frequency millimeter-wave (mm-wave) integrated transceivers and their building blocks such as oscillators, mixers, low-noise amplifiers, and power amplifiers. One of the popular mm-wave frequency bands is the 7 GHz unlicensed band available around 60 GHz, which is attractive for a variety of applications including wireless local area networks(WLANs), short-range high data-rate wireless personal area networks (WPANs), and vehicular radar. One of the critical challenges in the design of 60 GHz integrated transceivers is the local oscillator signal generation. One of the main objectives of this thesis is to present and experimentally validate techniques to achieve better phase noise for high frequency oscillators, especially for high data rate applications.This thesis studies the phase noise performance of a new rotary-wave coupled oscillator. The presented oscillator is a traveling-wave oscillator with a reduced phase distortion. This oscillator hybridizes the standing-wave oscillator and travelling-wave oscillator to take advantage of the benefits of each structure, i.e., low phase noise and low power consumption. The structure of this circuit is based on a travelling-wave oscillator tapped with four standing-wave oscillators along a transmission line to accurately provide multiphase outputs. This oscillator produces eight phases, 45° apart from each other. A proof-of-concept prototype oscillator, fabricated in a 0.13-μm CMOS technology, provides a −17.5 dBm tone at 67 GHz and achieves a 5.2 GHz tuning range (8%) while it consumes 43.2 mW from a 1.2-V supply. The measured phase noise is −87 dBc/Hz (−102 dBc/Hz) at 1 MHz (10 MHz) offset. As an application for this type of oscillator, a circular quadrature-amplitude modulation (QAM) small-signal polar transmitter is proposed and a proof-of-concept 16-level QAM modulator is designed and simulated. In this architecture, the proposed oscillator has been combined with an 8-to-1 multiplexer and four-level variable-gain amplifier to implement the QAM transmitter. Based on the post-layout simulation results, (which are in an excellent agreement with measured results for the oscillator block) the transmitter consumes 25% less power as compared to state-of-the-art 60-GHz transmitters with comparable performance.

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Synchronous clock distribution continues to be the dominant timing methodology for very large scale integration circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter. New techniques to reduce clock skew and jitter must be deployed to utilize the faster clock frequencies possible with future process technologies, especially in the presence of on-chip process-voltage-temperature (PVT) variations. This dissertation first proposes a pre-silicon design modification to symmetric clock buffers of traditional clock distribution networks. Specifically, clock performance is improved by targeting the critical clock edge (the edge activating rising edge-triggered flip-flops) while relaxing the requirements of the non-critical edge. This system uses alternating, asymmetric clock buffers to focus inverter resources on only one edge of the clock pulse; hence, it is called Single Edge Clocking (SEC). A novel re-design of the traditional clock buffer is proposed as a drop-in replacement for existing clock distribution networks, yielding timing performance improvements of over 20% in latency and skew, and up to 30% in jitter; alternatively, these timing advantages could be traded off to reduce clock buffer area and power by 33% and 12%, respectively. PVT variations, especially intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. Hence, active clock deskewing becomes necessary to tune out unwanted clock skew after chip fabrication. This dissertation proposes a post-silicon autonomous deskewing system using tunable buffers to dynamically reduce clock skew. The operation of a specially designed phase detector is described, and four such phase detectors are used to construct a stable, autonomously locking Quad Ring Tuning (QRT) configuration that effectively links together four distributed Delay-Locked Loops (DLLs) without the need for any system-level controller. This cyclic, unidirectional, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simple form of the two-level QRT system is presented for a generic H-tree distribution network, demonstrating stable locking behavior and more than 50% average reduction in full-chip clock skew.

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Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement.In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth.In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

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